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Designing network on-chip architectures in the nanoscale era , edited by José Flich, Davide Bertozzi

Boca Raton, FL , Chapman and Hall/CRC -- cop. 2011

1 vol. (xxxviii-490 p.) : ill., couv. ill. en coul. ; 24 cm

Chapman & Hall/CRC computational science series

978-1-439-83710-8 , rel.

Bibliogr. Index.

"Paving the way for the use of network on-chip architectures in 2015 platforms, this book presents the industrial requirements for such long-term platforms as well as the main research findings for technology-aware architecture design. It covers homogeneous design techniques and guidelines, including the solutions that are most appealing to the industry and best suited to meet the requirements of on-chip integration. Each chapter deals with a specific key architecture design, including fault tolerant design, topology selection, dynamic voltage and frequency scaling, synchronization, network on-chip resources exposed to the architecture, routing algorithms, and collective communication"--Provided by publisher

Networks on a chip

Systèmes sur puce

Architecture des ordinateurs

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